As disclosed in NPL 1 for example, such type of I/O system connects an I/O device (Input and Output device) in a single computer, and the computer is used for use of the I/O device. As shown in FIG. 1, the I/O system, for example, uses PCI Express (Registered Trademark; PCI Express is referred to as PCIe, hereinafter) and includes a root complex 102 that bridges a PCIe bus 13-0 and a memory bus 12 to CPU 101; a PCIe switch 10 that performs fan-out of the PCIe bus 13-0; and I/O devices 11-1 to 11-N (N is a natural number greater than or equal to two) that are connected to the PCIe switch 10 through PCI buses 13-1 to 13-N. In the PCIe, the side of the root complex 102 is referred to as the upstream and the side of the I/O devices 11-1 is referred to 11-N as the downstream.
The PCIe switch 10 includes an upstream PCI-PCI bridge 801 and downstream PCI-PCI bridges 902-1 to 902-N.
The upstream PCI-PCI bridges 801 is equipped with a configuration register (CFG REG) 8011 and the downstream PCI-PCI bridges 902-1 to 902-N are equipped with configuration registers (CFG REG) 9021-1 to 9021-N. The CFG REG 8011 and the CFG REGs 9021-1 to 9021-N each retain information about address spaces allocated to the devices that are connected to the more downstream sides than the bridges 801 and 902-1 to 902-N. The PCIe uses an ID number that is a combination of a bus number, a device number and a function number, and a memory space, as an address. Therefore, more specifically, the CFG REG 8011 and the CFG REGs 9021-1 to 9021-N each retain the lower and upper limits of a bus number allocated to the more downstream side than the bridges 801 and 902-1 to 902-N and the lower and upper limits of a memory space allocated to the more downstream side than the bridges 801 and 902-1 to 902-N.
As shown in FIG. 2, the I/O devices 11-1 to 11-N are mapped onto a physical memory space 14 of a computer to which the I/O devices 11-1 to 11-N are connected. In FIG. 2, the I/O devices 11-1 to 11-N are mapped between a map 1401-1 of the I/O device 11-1 and a map 1401-N of the I/O device 11-N on the physical memory space 14.
The I/O system having such configuration operates in the following manner.
When software that runs on the CPU 101 accesses, for example, the I/O device 11-1 of the I/O devices 11-1 to 11-N, the CPU 101 issues a command to the root complex 102. Following the protocol standardized in PCIe, the root complex 102 generates and issues TLP (Transaction Layer Packet). In the destination of the TLP header, the ID number allocated to the I/O device 11-1 to be accessed or the memory space on which the I/O device 11-1 is mapped is recorded. The PCIe switch 10 receives the TLP, and compares the address recorded in the header with information held by CFG REG 8011. If the destination of the TLP is connected to the downstream side of the upstream PCI-PCI bridge 801, the PCIe switch 10 then compares the address with information held by CFG REG 9021-2 and transmits the TLP to the I/O device 11-1 which is the destination of the TLP.
On the other hand, if the I/O device 11-1t of the I/O devices 11-1 to 11-N issues TLP to the CPU 101, the opposite procedure to the above procedure is performed. In this case, the PCIe switch 10 that receives the TLP from the I/O device 11-1 checks CFG REG 9021-1 and determines that the destination of the TLP does not correspond to the device connected to the downstream side of the downstream PCI-PCI bridge 902-1 that receives the TLP. Subsequently, the PCIe switch 10 compares the address with information held by CFG REG 8011 and determines that the destination of the TLP does not correspond to the device connected to the downstream side of the upstream PCI-PCI bridge 801. Then, the PCIe switch 10 transfers the TLP to the root complex 102. Therefore, the TLP is transmitted to the CPU 101.
According to DMA (Direct Memory Access), for example, the I/O device 11-1 of the I/O devices 11-1 to 11-N directly writes or reads data to or from a memory 103 of the computer. In this case, for example, the I/O device 11-1 regards the address of the memory onto which the memory 103 is mapped, as destination, generates TLP and then accesses the memory 103. At this time, the TLP transfer procedure of the I/O system is the same as the procedure of the I/O device 11-1 accessing the CPU 101.